Semiconductor device with sense structure

ABSTRACT

A power semiconductor device is described with a plurality of cells divided into power cells ( 14 ) and sense cells ( 16 ). A plurality of groups ( 30, 32 ) of sense cells ( 16 ) are provided. The device allows for compensation of effects caused at the edges of the groups of sense cells ( 16 ).

The invention relates to a semiconductor device with sense structure,and in particular to a power semiconductor device having a senseterminal, as well as to a system including the power semiconductordevice.

A known example of a prior art power semiconductor device is a Sensemetal-oxide-semiconductor field effect transistor (MOSFET) structure,conventionally shortened to SenseMOS. The SenseMOS has the source, gateand drain of a conventional MOS together with a further sense terminalthat provides a sense current which should be proportional to the loadcurrent. In an ideal SenseMOS structure the sense current should beproportional to the load current under all operating conditions.

The current output on the sense terminal can be used, for example, tomake a current protected switch. The sense current may be compared to apredetermined current, and when the sense current becomes too large, thevoltage applied to the gate of the SenseMOS structure is reduced toreduce the output current.

An example of a SenseMOS structure and its use in a current-protectedswitch is described in WO 96/12346 to Philips Electronics NV. The devicehas a number of MOSFET cells—a few of these cells are connected to thesense terminal to supply the sense current and the rest are connected toa main output terminal to supply the main output current used to drive aload.

It will be appreciated by the skilled person that it is important insuch applications that the sense current should accurately track themain current over a wide range of conditions. It is also highlydesirable that the ratio of the current in the main cells to that in thesense cells should be the ratio of the number of cells. This means thatduring operation the conditions in every cell should be as identical aspossible, and in particular the conditions in the small number of sensecells should match those in the main cells. However, such accuratematching is not always possible, especially when using small cell sizes(less than about 5-6 μm, for example), without using expensivemanufacturing technology.

The invention aims to address this difficulty and allow for moreaccurate tracking of the main current.

According to the invention there is provided a power semiconductordevice, comprising: first and second main terminals, at least one ofwhich is for coupling a load; a control terminal; and a semiconductorbody having opposed first and second major surfaces and a plurality ofcells arranged as a lattice across the first major surface of thesemiconductor body, the cells being divided into main cells and sensecells, each of the cells having a gate or base connected to the controlterminal; wherein each of the main cells is connected in parallelbetween the first and second main terminals to couple the first andsecond main terminals under the control of the control terminal; thepower semiconductor device further comprises first and second senseterminals; the sense cells are divided into a plurality of groups ofsense cells each arranged across the lattice in a pattern, each group ofsense cells being connected in parallel between a respective senseterminal and the second main terminal; and a first group of sense cellsis arranged across the lattice in a pattern having a different ratio ofedge to inner cells to a second group of sense cells, inner sense cellsbeing cells surrounded by other sense cells of the group and edge sensecells being arranged on the edge of the group of sense cells.

The inventors have realised that a problem in prior art devices is edgeeffects. In other words, the electrical conditions in the cells at theboundary between main and sense cells are often not identical to theelectrical conditions in the bulk of the cells. This problem isparticularly acute when there are dummy cells, not connected to eitherthe main electrode or a sense electrode, between the main and the sensecells. These unconnected dummy cells affect the current in the edgecells, as will be explained in more detail below.

Such edge effects are generally very minor in the main cells, where thenumber of cells at the edge of the group of main cells is very smallcompared with the total number of cells. However, there are in general amuch smaller number of sense cells and edge effects can become highlysignificant in the sense cells. This, in prior art devices, means thatthe sense cells do not accurately track the current in the main cells.

The semiconductor device according to the invention compensates for thisedge effect by providing two distinct groups of sense cells andrespective sense terminals, the groups of sense cells being arranged inthe lattice of cells in patterns such that the two groups of sense cellshave different ratios of edge cells to inner cells. The two outputcurrents then provide sufficient information to act both as a measure ofthe current in the inner cells and also as a measure of the current inthe edge cells.

Preferably, the number of edge cells in the first group of sense cellssubstantially matches that in the second group. This makes itparticularly easy to correct for the effects of edge cells.

In a particularly convenient arrangement a first group of sense cells isarranged in a pattern having at least 40% preferably 50% or even 80%edge cells—this may be achieved, for example, by using a line of cellsas the sense cells. The output of this first group of sense cells thenprovides a measure of the current in the edge cells. A second group ofsense cells is arranged to have a greater number of inner cells,although it will inevitably have edge cells as well. The current outputfrom this second group of sense cells may then be corrected for theeffect of the edge cells using the current output from the first group.This corrected, or compensated, signal then represents a much moreaccurate measure of the current in the main cells.

The invention is particularly applicable to power MOSFETs in which thecells are MOS cells having gate source and drain. The source and drainof main cells are connected to the first and second main terminals andthe source and drain of sense cells of a group are connected between thefirst main terminal and the respective sense terminal of that group.

In embodiments, the MOSFETs may be trench MOSFETs. The skilled personwill realise that the invention is not restricted to trench MOSFETs andthe skilled person will be familiar with a number of other useful cellstructures, including for example vertical and lateral MOSFET structuresand even arrays of insulated gate bipolar devices.

The cells may be of any convenient shape, for example hexagonal, square,or stripes.

The power semiconductor device may be packaged as a discrete powersemiconductor device.

The invention also relates to a semiconductor arrangement including thesemiconductor device and further comprising a drive circuit having anoutput connected to the control terminal for driving the controlterminal and a compensation circuit.

The compensation circuit preferably has first and second sense inputsconnected directly or indirectly to the first and second sense terminalsrespectively and an output connected to the drive circuit forcontrolling the drive circuit, wherein the compensation circuit outputsto the drive circuit a measure of the current in inner sense cellsobtained from the currents on the first and second sense inputs.

The compensation circuit may include a reference sub-circuit with aninput connected to the first sense terminal and an output supplying areference voltage, wherein the current from the first sense terminal isapplied across a resistor to increase the reference voltage linearlywith the current from the first group of sense cells.

The compensation circuit may further include a sense sub-circuit with aninput connected to the second sense terminal connected to the secondgroup of sense cells and a compensation input connected to the output ofthe reference sub-circuit, and an output supplying a compensated sensecurrent signal to the drive circuit input for controlling the drivecircuit to limit the current output by the power semiconductor device.The current from the second group of sense cells may be applied across alike resistor to that in the reference sub-circuit and the voltagegenerated across the like resistor compared with the input from thereference sub-circuit to generate the output.

In this way, when the number of edge cells in the first and secondgroups of sense cells is the same, the effect of the edge cells iscompensated.

In a particular embodiment, the cells are MOS cells of predeterminedfirst conductivity type having gate, source and drain, the drains of themain and sense cells being connected in common to the first terminal,and the source of the main cells being connected to the second terminalconnected in turn to a source voltage rail (V_(ss)).

The drive circuit may include a FET of the first conductivity typehaving its source connected to the source voltage rail, its drainconnected to the control terminal of the power semiconductor device andto a gate drive circuit.

The reference sub-circuit may include a FET of the first conductivitytype having its source connected to the source voltage rail through aresistance, its drain connected through a resistance to a logic supply,its gate connected to the drain and to the output of the referencesub-circuit, and wherein the input of the reference sub-circuit isconnected to the source of the reference sub-circuit FET for supplyingthe current output on the first sense terminal to the referencesub-circuit.

The sense sub-circuit may include a FET of the first conductivity typehaving its source connected to the source voltage rail through aresistance, its drain connected through a resistance to a logic supply,its gate connected to the output of the reference sub-circuit, andwherein the input of the sense sub-circuit is connected to the sourcefor supplying the current output on the second sense terminal to thesense sub-circuit, for comparing the current with a value set by thereference sub-circuit and outputting a signal to the drive circuit.

The resistances between the FETs of the reference and sense sub-circuitsand the source voltage rail are preferably matched sense resistors.

The semiconductor arrangement may be provided as an integrated packageincluding the compensation circuitry.

Note that the specific compensation circuit described is not the onlypossibility and the skilled person will be able to carry out the samefunctions in many other ways. For example, an operational amplifier maybe used.

For a better understanding of the invention, embodiments will now bedescribed, purely by way of example, with reference to the accompanyingdrawings, in which:

FIG. 1 shows a cross-sectional side view of a SenseMOS according to theinvention;

FIG. 2 shows a first arrangement of a group of sense cells in anarrangement according to the invention;

FIG. 3 shows a second arrangement of a group of sense cells in anarrangement according to the invention;

FIG. 4 shows schematically the terminals of a SenseMOS according to theinvention;

FIG. 5 shows a circuit according to the invention; and

FIG. 6 shows a packaged semiconductor device according to the invention.

It should be noted that the drawings are not to scale. Further, notethat like components are given like reference numerals in differentfigures.

Referring to FIG. 1, a cross-section through a trenchMOS structure isshown. An n+ substrate 2 has an n− epilayer 4 formed on its first majorsurface 114 and a drain contact 20 on its second major surface 116. Then+ substrate 2 constitutes the drain connected to drain contact 20.

A plurality of cells 12 are formed on the epilayer extending across thefirst major surface, the cells being defined by insulated trenches 6filled with polysilicon gates 8. Source regions 10 and p-body regions 11are formed between the trenches 6 in each cell 12.

Most of the cells are main cells 14, and the source regions 10 and thep-body regions 11 of these cells are connected in parallel to a mainmetallisation 22. FIG. 1 also shows a group of sense cells 16—the sourceregions 10 and p-body regions 11 of the sense cells are connected inparallel to sense metallisation 24.

When a small cell pitch is used then photolithographic tolerances do notallow sufficient space to contact reliably the source 10 and p-bodyregion 11 of all the cells. Therefore, dummy cells 18 are used betweensense cells 16 and the main cells 14—these cells are not connected andaccordingly do not operate as normal cells. The cells adjacent to thesedummy cells 18 will be referred to as edge cells 28.

The current paths 26 of the device of FIG. 1 are illustratedschematically. No source current flows in the dummy cell 18, and so lesscurrent flows along the gates 8 in the adjacent edge cells 28. Thisreduces current crowding effects in these cells and offer a lowerresistance path. The net effect is that the edge cells 28 at theinterface conduct a very different current from those in the middle ofthe array, which can have a very significant effect on the sensecurrent. This effect is exacerbated if the ratio of main cells to sensecells is very high, as it can be.

FIGS. 2 and 3 show top views of sense cell clusters used in thisembodiment of the invention. FIG. 2 shows a first sense cell cluster 30having above 50% edge cells 28 and FIG. 3 shows a second sense cellcluster 32 having both edge cells 28 and inner sense cells 34.

Note that the number of edge cells is the same in each of the two sensecell clusters 30, 32.

The power semiconductor device in the first embodiment is packaged asindicated schematically by package 51 shown schematically in FIG. 4. Inthe arrangement shown, the power semiconductor device has first andsecond sense cell groups 30,32 each connected in parallel tocorresponding first and second sense terminals 40,42. The common draincontact 20 is connected to a first main terminal 44 and a second mainterminal 46 is connected to the main cells 16. Control terminal 48 isconnected in common to the gates.

A circuit using this arrangement is shown by way of example in FIG. 5.

The first main terminal 44 is connected to load 52. The second mainterminal 46 is connected to a source voltage rail 53.

The circuit includes reference sub-circuit 54 having input 56 connectedto the first sense terminal 40 and having reference output 58. Thissub-circuit 54 is connected in turn to sense sub-circuit 60 having input62 connected to the second sense terminal 42 and control input 64connected to the reference output 58. The sense sub-circuit has output66. Note that the outputs and inputs may be nothing more than a track ona semiconductor substrate.

Both reference and sense sub-circuits are connected between logic supplyrail 68 and the source voltage rail 53.

The reference sub-circuit 54 includes an n-type MOSFET 80 having itssource connected directly to input 56 and through resistor 82 to thesource voltage rail 53. The drain is connected through resistor 84 tothe logic supply rail 68, and also to the gate which is in turnconnected to output 58.

The sense sub-circuit 60 includes an n-type MOSFET 90 having its sourceconnected directly to input 62 and through resistor 92 to the sourcevoltage rail 53. The drain is connected through resistor 94 to the logicsupply rail 68. The gate is connected to input 64 and hence to theoutput 58 of reference sub-circuit 54. The output 66 of the sensesub-circuit is taken from the drain.

The other part of the circuit is the drive circuit 70 having a furthern-MOSFET 96 having its gate connected to the drive input 74 and hence inturn connected to the output 66 of the sense sub-circuit. The drain isconnected to a gate drive (not shown) through resistor 98. The source isconnected to source voltage rail 53. The output 76 of the drive circuitis taken from the drain and connected to the input 48 of the powertransistor 50.

In operation, the circuit operates by comparing the voltage of then-MOSFET 80 in the reference sub-circuit 54 with voltage at the gate ofthe n-MOSFET 90 in the sense sub-circuit 60. If the latter is too high,then the voltage to the gates of the MOSFET 96 of the drive circuit 70and hence on the power MOSFET 50 is reduced until equilibrium isestablished. The circuit thus operates as a current limiting circuit.

The circuit compensates for the edge effect by injecting at the sourceof MOSFET 80 in the reference sub-circuit 54 the current from the senseterminal 40. This raises the gate voltage on output 58 of the referencesub-circuit 54 by an amount related to the current in edge cells. Thesense current from sense terminal 42 is injected at the source of MOSFET90 in the sense sub-circuit, which raises its voltage by thecontributions from the normal cells and the edge cells. The voltagecontributions from edge cells will cancel out, since both the first andsecond groups have the same number of edge cells and resistors 82, 92are matched. The resultant correction signal applied to the drivecircuit will only have contributions from the inner cells.

The ratio of load current to sense current should not vary very muchwith temperature since the properties of the edge cells will vary inparallel to the properties of other cells. The resistors 82, 92 are madeof polysilicon which has a very low temperature coefficient.

Alternatively, the SenseMOS 50 may be used as a discrete devicecontrolled by an operational amplifier with a virtual earth, as will beappreciated by the skilled person.

Because the edge effects are compensated for, it becomes possible to usesmaller cell pitches in SenseMOS structures necessitating the use ofdummy cells. These lower cell pitches in turn deliver the benefit of alower specific drain source resistance in the on-state (R_(ds) (on))whilst still achieving an accurate load to sense current ratio.

In a second embodiment, the whole circuit of FIG. 5 except the load isincorporated in a single device package as indicated schematically bypackage 100 in FIG. 5.

The invention may be used in discrete devices, illustrated schematicallyin FIG. 6. The semiconductor die 102 is mounted on a lead frame 104 andhoused in a package 101. The example shown is a seven pin package, inwhich terminals 40, 42, 44, 46, 48, 110 and 112 are electricallyconnected to the die by wires 106. In the illustrated device, main celland sense cell Kelvin terminals 110 and 112 are provided connected onthe chip to the sources 10 of the main cells 14 and sense cells 16respectively. This allows the voltage at the sources 10 to be measuredmore accurately. The substantial current output on main terminal 46causes voltage to be dropped and hence the voltage measured on terminal46 is not an accurate measure of the voltage at the source. The use ofKelvin terminals 110, 112 to measure voltage without drawing substantialcurrent alleviates this problem.

Applications for the invention include those which require load andsense current to be maintained very accurately over a wide range of loadcurrent, temperature and supply voltage.

From reading the present disclosure, other variations and modificationswill be apparent to persons skilled in the art. Such variations andmodifications may involve equivalent and other features which arealready known in the design, manufacture and use of semiconductordevices and which may be used in addition to or instead of featuresdescribed herein. Although claims have been formulated in thisapplication to particular combinations of features, it should beunderstood that the scope of disclosure also includes any novel featureor any novel combination of features disclosed herein either explicitlyor implicitly or any generalisation thereof, whether or not it mitigatesany or all of the same technical problems as does the present invention.The applicants hereby give notice that new claims may be formulated toany such features and/or combinations of such features during theprosecution of the present application or of any further applicationsderived therefrom.

In particular, the invention can be used with trench cells of variousshapes and arrangements. Nor is the invention limited to trenchMOSFETs—the skilled person will readily realise how to realise theinvention in alternative cell-based structures, including for examplelateral MOSFETs, other types of vertical MOSFETs and even otherstructures.

Further, although the described embodiment uses two groups of sensecells and it is not generally desirable to have too many groups of sensecells, the invention may include further groups of sense cells ifrequired.

1. A power semiconductor device, comprising: first and second mainterminals, at least one of which is for coupling a load; a controlterminal; and a semiconductor body having opposed first and second majorsurfaces and a plurality of cells arranged as a lattice across the firstmajor surface of the semiconductor body, the cells being divided intomain cells and sense cells, each of the cells having a gate or baseconnected to the control terminal wherein each of the main cells isconnected in parallel between the first and second main terminals tocouple the first and second main terminals under the control of thecontrol terminal; the power semiconductor device further comprises firstand second sense terminals; the sense cells are divided into a pluralityof groups of sense cells each arranged across the lattice in a pattern,each group of sense cells being connected in parallel between arespective sense terminal and the second main terminal; and a firstgroup of sense cells is arranged across the lattice in a pattern havinga different ratio of edge to inner cells to a second group of sensecells, inner sense cells being cells surrounded by other sense cells ofthe group and edge sense cells being arranged on the edge of the groupof sense cells.
 2. A semiconductor device according to claim 1 whereinthe number of edge sense cells in the first and second groups of sensecells is substantially identical.
 3. A semiconductor device according toany preceding claim wherein the cells are MOS cells including agate-connected to the control terminal, and a source and drain, thesource and drain of main cells being connected to the first and secondmain terminals and the source and drain of sense cells of a group beingconnected between the second main terminal and the respective senseterminal.
 4. A semiconductor device according to claim 3 wherein thecells are trench MOSFET cells.
 5. A semiconductor device according toclaim 1 further comprising a Kelvin terminal connected to the source ofthe main cells.
 6. A semiconductor arrangement comprising: asemiconductor device according to claim 1; a drive circuit having aninput and an output, the output being connected to the control terminalfor driving the control terminal; and a compensation circuit havingfirst and second sense inputs connected directly or indirectly to thefirst and second sense terminals, respectively, and an output connectedto the drive circuit for controlling the drive circuit, wherein thecompensation circuit outputs to the drive circuit input a signal basedon the current in inner sense cells, obtained from the currents on thefirst and second sense inputs.
 7. A semiconductor arrangement accordingto claim 6 wherein: the compensation circuit includes a referencesub-circuit with an input connected to the first sense terminalconnected to the first group of sense cells, and an output supplying areference voltage, wherein the current from the first sense terminal isapplied across a resistance to increase the reference voltage linearlywith the current from the first group of sense cells; the compensationcircuit further includes a sense sub-circuit which has an inputconnected to the second sense terminal connected to the second group ofsense cells wherein the current from the second group of sense cells isapplied across a like resistance to that in the reference sub-circuit togenerate a voltage; and the sense sub-circuit has a compensation inputconnected to the output of the reference sub-circuit, the sensesub-circuit being operable to compare the voltage input on thecompensation input with that generated across the like resistor togenerate an output supplying a compensated sense current signal to thedrive circuit input for controlling the drive circuit to limit thecurrent output by the power semiconductor device.
 8. A semiconductorarrangement according to claim 7 wherein: the power semiconductor devicehas MOS cells of predetermined first conductivity type having gate,source and drain, the gates of the cells being connected in parallel tothe control terminal, the drains of the main and sense cells beingconnected in common to the first main terminal and the sources of themain and sense cells being connected to the second main terminal andsense terminals respectively; wherein the second main terminal isconnected to a source voltage rail (V_(SS)); the drive circuit includesa FET of the first conductivity type having its source connected to thesource voltage rail, its drain connected to the control terminal of thepower semiconductor device and to a gate drive circuit; the referencesub-circuit includes a FET of the first conductivity type having itssource connected to the source voltage rail through the resistance, itsdrain connected through a resistance to a logic supply, its gateconnected to its drain and to the output of the reference sub-circuit,and wherein the input of the reference sub-circuit is connected to thesource of the reference sub-circuit FET for supplying the current outputon the first sense terminal to the reference sub-circuit; and the sensesub-circuit includes a FET of the first conductivity type having itssource connected to the source voltage rail through the resistance, itsdrain connected through a resistance to a logic supply, its gateconnected to the output of the reference sub-circuit, and wherein theinput of the sense sub-circuit is connected to the second sense terminalfor comparing the current output on the second sense terminal with avalue set by the reference sub-circuit and outputting a signal to thedrive circuit.
 9. A semiconductor arrangement according to any of claims6 to 8 housed in a single package.
 10. A semiconductor arrangementaccording to any of claims 6 to 8 wherein the first main terminal isconnected to a load.
 11. A semiconductor device according to claim 1wherein the first group of sense cells includes at least as many edgecells as inner cells, and wherein the second group of sense cellsincludes more inner cells than edge cells.
 12. A semiconductor deviceaccording to claim 11 wherein at least 80% of the sense cells of thefirst group of sense cells are edge cells.
 13. A semiconductor deviceaccording to claim 11 wherein the number of edge sense cells in thefirst and second groups of sense cells is substantially identical.
 14. Asemiconductor device according to claim 13 further including acompensation circuit that uses a current output from the first group ofsense cells to compensate a current output from the second group ofsense cells to thereby provide a signal reflective of the current ininner sense cells.